Memory devices are typically provided as internal storage areas in the computer. The term memory identifies data storage that comes in the form of integrated circuit chips. There are several different types of memory used in modern electronics, one common type is RAM (random-access memory). RAM is characteristically found in use as main memory in a computer environment. RAM functions as a read and write memory; that is, you can both write data into RAM and read data from RAM. This is in contrast to read-only memory (ROM), which permits you only to read data. Most RAM is volatile, which means that it requires a steady flow of electricity to maintain its contents. As soon as the power is turned off, whatever data was in RAM is lost. Computers almost always contain a small amount of ROM that holds instructions for starting up the computer.
EEPROM (electrically erasable programmable read-only memory) and Flash memories are special types of non-voF31Flatile ROMs that can be written and erased. A Flash memory is a type of EEPROM that is typically erased and reprogrammed in blocks instead of a single bit or one byte (8 or 9 bits) at a time. Flash and EEPROM memories may use floating gate technology or trapping technology non-volatile memory cells. Floating gate cells include source and drain regions that are laterally spaced apart to form an intermediate channel region. The source and drain regions are typically formed in a common horizontal plane of a silicon substrate. The floating gate, generally made of doped polysilicon, is disposed over the channel region and is electrically isolated from the other cell elements by oxide. The non-volatile memory function for the floating gate technology is created by the absence or presence of charge stored on the isolated floating gate. In floating node/embedded trap non-volatile memory cells, the stored charge is “trapped” and stored in a non-conductive trapping layer. One example of this trapping technology that functions as a non-volatile memory is the silicon-oxide-nitride-oxide-silicon (SONOS) architecture. In the SONOS architecture, the nitride trap layer can capture and store electrons or holes in order to act as a non-volatile memory.
The memory cells of both an EEPROM memory array and a Flash memory array are typically arranged into either a “NOR” architecture (each cell directly coupled to a bit line) or a “NAND” architecture (cells coupled into “strings” of cells, such that each cell is coupled indirectly to a bit line and requires activating the other cells of the string for access).
A problem in Flash/EEPROM floating gate and SONOS memory cell arrays is that voltage scalability affects the minimum cell size, and consequently the overall memory density of any resulting array. Both SONOS and floating gate Flash/EEPROM memories consume relatively high power compared to other memory technologies, requiring external or on-chip high voltage/current supplies for programming and erase operations. Due to the high programming voltage requirement, neighboring cells must be separated sufficiently apart (significantly greater than the minimum feature size) so as not to be disturbed by the capacitive coupling effect during programming of the active cell. This problem is more severe with scaling of the feature size capability, affecting cell density. In addition, the high programming/erase voltages diminish device endurance and retention by damaging the materials of the memory cell and generating flaws. As integrated circuit processing techniques improve, manufacturers try to reduce the feature sizes of the devices produced and thus increase the density of the IC circuits and memory arrays. Additionally, with progressive scaling of feature size, fundamental device leakage issues such as short-channel effects and gate dielectric leakage need to be contained in order to take advantage of scaling.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for low power scalable non-volatile memory cell devices.